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DDR3 UDIMM kumbukumbu ya moduli

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Aina ya malipo:

L/C,T/T,D/A

Incoterm:

FOB,EXW,CIF

Min. Amri:

1 Piece/Pieces

Usafiri:

Ocean,Air,Express,Land

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Maelezo ya bidhaa

Sifa za Bidhaa
Uwezo wa Ugavi na Taarifa za Ziada
Ufungaji & Utoaji

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Overview

Sifa za Bidhaa

Mfano wa Mfano.: NSO4GU3AB

Uwezo wa Ugavi na Taarifa za Ziada

Usafiri: Ocean,Air,Express,Land

Aina ya malipo: L/C,T/T,D/A

Incoterm: FOB,EXW,CIF

Ufungaji & Utoaji

Kuuza Vitengo:: Piece/Pieces

4GB 1600MHz 240-pin DDR3 Udimm

Historia ya marekebisho

Revision No.	History	Draft Date	Remark
1.0	Initial Release	Apr. 2022

Kuagiza meza ya habari

Model	Density	Speed	Organization	Component Composition
NS04GU3AB	4GB	1600MHz	512Mx64bit	DDR3 256Mx8 *16

Maelezo
Hengstar Unbuffered DDR3 SDRAM DIMMs (Kiwango cha data mara mbili cha data Synchronous DRAM mbili za kumbukumbu za kumbukumbu) ni nguvu ya chini, moduli za kumbukumbu za kasi za juu ambazo hutumia vifaa vya DDR3 SDRAM. NS04GU3AB ni 512m x 64-bit mbili kiwango cha 4GB DDR3-1600 CL11 1.5V SDRAM Bidhaa isiyo na kipimo ya DIMM, kulingana na sehemu kumi na sita za 256m x 8-bit FBGA. SPD imeandaliwa kwa saa ya Jedec Standard DDR3-1600 ya 11-11-11 saa 1.5V. Kila 240-pini DIMM hutumia vidole vya mawasiliano ya dhahabu. DIM ya SDRAM ambayo haijakamilika imekusudiwa kutumiwa kama kumbukumbu kuu wakati imewekwa katika mifumo kama PC na vituo vya kazi.

Vipengele
Ugavi wa Nguvu: VDD = 1.5V (1.425V hadi 1.575V)
VDDQ = 1.5V (1.425V hadi 1.575V)
800MHz FCK kwa 1600MB/sec/pini
8 Benki ya ndani ya kujitegemea
Programmable CAS latency: 11, 10, 9, 8, 7, 6
Programmable kuongeza latency: 0, cl - 2, au cl - 1 saa
8-bit kabla ya kuchota
 Urefu: 8 (interleave bila kikomo chochote, mlolongo na anwani ya kuanza "000" tu), 4 na TCCD = 4 ambayo hairuhusu kusoma au kuandika [ama kwenye kuruka kwa kutumia A12 au MRS]
Bi-mwelekeo wa data tofauti
Internal (ubinafsi) calibration; Urekebishaji wa ndani wa ndani kupitia pini ya ZQ (RZQ: 240 ohm ± 1%)
Kukomesha kumaliza kwa kutumia pini ya ODT
Average Kipindi cha kuburudisha 7.8US chini kuliko tcase 85 ° C, 3.9US kwa 85 ° C <TCase <95 ° C
Synchronous Reset
Matokeo ya nguvu ya data-inayoweza kubadilika
Fly-na topolojia
PCB: Urefu 1.18 ”(30mm)
Rohs inafuata na halogen

Vigezo muhimu vya wakati

MT/s	tRCD(ns)	tRP(ns)	tRC(ns)	CL-tRCD-tRP
DDR3-1600	13.125	13.125	48.125	2011/11/11

Jedwali la anwani

Configuration	Refresh count	Row address	Device bank address	Device configuration	Column Address	Module rank address
4GB	8K	32K A[14:0]	8 BA[2:0]	2Gb (256 Meg x 8)	1K A[9:0]	2 S#[1:0]

Maelezo ya pini

Symbol	Type	Description
Ax	Input	Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information.
BAx	Input	Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
CKx, CKx#	Input	Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx	Input	Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx	Input	Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins.
ODTx	Input	On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Par_In	Input	Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#	Input	Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
RESET#	Input (LVCMOS)	Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#	Input	Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder.
SAx	Input	Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL	Input	Serial communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx	I/O	Check bits: Used for system error detection and correction.
DQx	I/O	Data input/output: Bidirectional data bus.
DQSx, DQSx#	I/O	Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-alig
SDA	I/O	Serial sensor/SPD EEPROM on the I2C bus.
TDQSx, TDQSx#	Output	Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function.
Err_Out#	Output (open drain)	Parity error output: Parity error found on the command and address bus.
EVENT#	Output (open drain)	Temperature event: The EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded.
VDD	Supply	Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The component VDD and VDDQ are connected to the module VDD.
VDDSPD	Supply	Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA	Supply	Reference voltage: Control, command, and address VDD/2.
VREFDQ	Supply	Reference voltage: DQ, DM VDD/2.
VSS	Supply	Ground.
VTT	Supply	Termination voltage: Used for control, command, and address VDD/2.
NC	–	No connect: These pins are not connected on the module.
NF	–	No function: These pins are connected within the module, but provide no functionality.

Vidokezo : Jedwali la maelezo ya pini hapa chini ni orodha kamili ya pini zote zinazowezekana kwa moduli zote za DDR3. Pini zote zilizoorodheshwa Mei isiungwa mkono kwenye moduli hii. Tazama kazi za pini kwa habari maalum kwa moduli hii.

Mchoro wa kuzuia kazi

4GB, moduli ya 512mx64 (2Rank ya x8)

Kumbuka:

1. Mpira wa ZQ kwenye kila sehemu ya DDR3 umeunganishwa na kontena ya nje ya 240Ω ± 1% ambayo imefungwa chini. Inatumika kwa hesabu ya kukomesha kwa sehemu ya kufa na dereva wa pato.

Vipimo vya moduli

Mtazamo wa mbele

Vidokezo:
1. Vipimo vyote viko katika milimita (inchi); Max/min au kawaida (typ) ambapo imebainika.
2.Tolerance juu ya vipimo vyote ± 0.15mm isipokuwa ilivyoainishwa vingine.
3. Mchoro wa mwelekeo ni wa kumbukumbu tu.

Jamii za Bidhaa : Vifaa vya moduli za viwandani

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